In recent years, with increasingly large integration of a semiconductor device, large integration of semiconductor elements themselves constituting the semiconductor device is also required. Particularly, in integration technologies of recent semiconductor devices, in addition to integration of semiconductor elements themselves, integration of heterogeneous elements are required.
Two methods, the SoC (System on Chip) technology and the SiP (System in Package) technology, are typically known as methods of highly integrating semiconductor elements having heterogeneous functions. The SoC technology is an integration method of forming a plurality of elements as one chip such as system LSI. Unfortunately, while the SoC technology can increase the integration density of elements, device elements that can be integrated are limited. For example, it is difficult to combine device elements made of different crystal structure, such as GaAs device and Si device, due to different fabrication processes. In addition, the SoC technology has a problem of a longer design period when a new device is realized, which requires large investment for development of the new device.
In contrast to the SoC technology, the SiP technology is a method of individually forming each semiconductor chip and then mounting each chip individually on an integration substrate (interposer substrate). Because each semiconductor chip can individually be fabricated, no restrictions are imposed on fabrication process of elements to be integrated. Further, when a new SiP is realized, because chips already existing can be used, the design period can be shortened and therefore, development costs can be reduced compared to SoC. Unfortunately, however, the integration density of elements depends on the wiring density of an interposer substrate on which each semiconductor chip is mounted and thus, it is difficult to make integration density of elements higher than compared with the SiP technology.
Therefore, a pseudo-SoC technology is proposed. The pseudo-SoC is set up with heterogeneous chips embedded in epoxy resin, planar layer and redistributed layer. The heterogeneous chips are chips such as MEMS (Micro Electro Mechanical System), driver, CPU (Central Processing Unit) and memory. The heterogeneous chips are tested and selected as KGD (Known Good Die) chips before being redistributed and integrated to a chip-redistributed wafer. Thus heterogeneous device elements are integrated in one chip at a reduced cost, same as SiP. By forming redistributed layer with the most advanced semiconductor process, redistributed layer with fine pitch can be achieved. Thus integration with high density can also be achieved, same as SoC.
An improvement of mechanical strength is required in the pseudo-SoC technology. Particularly, when the size of heterogeneous chips to be arranged is large or when the number of heterogeneous chips to be arranged is large, the improvement of mechanical strength becomes more difficult.